Marwan Sledge

Mountain View, California, US

Passionate tech entrepreneur with music chops
Marwan's Skills
Technical
Product Management
User Experience
Strategy
Sales
Operations
Marketing
Management
Design
Business Development
Fundraising
Finance
Background

Startup Experience

First time founder

Quote

When you innovate, you've got to be prepared for everyone telling you you're nuts. - Larry Ellison

Work Experience

iOS Power Engineer

Apple

August 2013 - August 2015

• Responsible for characterizing and optimizing power for various features and components (VRR, Force Touch, Display subcomponents, WiFi, Slide Over, Battery Life Monitor, etc) across all iOS devices • Wrote test plans and test cases focus around power consumption of various components • Helped maintain and expand automation platforms and infrastructure (Python) • Tweaked mathematical models for Battery Life Monitor & Powerlog • Oversaw test execution and data validation for weekly reporting for upper level management

Post-Silicon Validation Engineer

Intel

October 2011 - March 2013

• Validated features server processors (Ivybridge server) and client (Ultrabook) products (Haswell) ◦ Responsible for validating various features inside the uncore for each project ◦ Also responsible for triage and runtime efficiency of automation systems in test execution • Also worked in Performance Validation for Jaketown (Sandy Bridge server) • Developed extensive experience in Python ◦ Co-developed a tool designed to merge multiple tests into a single suite to save execution time ◦ Developed a boot script to merge test content and intelligently run that content automatically • Received 4 SRA awards recognizing my contributions to the System Validation team

Technical Summer Intern

NASA

June 2005 - August 2005

Undergrad Intern - Technical

Intel

May 2009 - August 2009

• Worked in Pre-Silicon Validation for Haswell (the next microarchitecture after Sandy Bridge) • Added features to a random test generator in a Pre-Silicon automation environment • Wrote various algorithms in Perl, Python, and IA32 / IA64 assembly • Implemented EPT paging constructs for the test generator

Undergrad Intern - Technical

Intel

June 2008 - August 2008

• Worked in Interconnect Design for Westmere (the die shrink of Nehalem) • Designed a new automated flow to help keep future milestones on schedule • Earned an "Outstanding" (5/5) in my performance review and an SRA award

Education

Cornell University

Electrical & Computer Engineering

2006 - 2011

Cornell University

Minor in Music

2006 - 2011

Accelerator/Incubator

NVIDIA Inception

2016